Integrated circuit memory devices store information in arrays of cells arranged in addressable rows and columns. During fabrication of these devices, one or more defects may occur and prevent the proper performance of the memory circuit. Some types of defects may be analyzed and corrected on the device. Other types of defects may not be corrected and are the cause of the failed devices. Distribution of defects in any memory device may be random. The yield of good devices per wafer can be improved over time by eliminating the causes of such defects.
Integrated circuit memories are being made with increasing bit densities, smaller storage cell sizes, and more input/output (I/O) pins, as the generations of new memory devices are designed and built. As a result, devices are more susceptible to defects caused by processing variations and reduced tolerances. Testing must be done to detect and correct the defects so that sufficiently high device yields are achieved for profitable production.
Problems arise in testing integrated circuit devices with greater densities and with more input/output pins.
Memory devices which have more storage cells require longer task sequences to be run. Therefore, more device tester time is required for testing each device. Also, end users desire to use more and more I/O pins per device. Such wide I/O pin devices inherently limit the number of such devices which can be tested at one time on a device tester. Thus, fewer of the wide I/O devices can be tested simultaneously on one device tester. Both the increase in test time and the reduced number of devices that can be tested at one time make testing an ever-increasing expense.
In response to the dilemma which has developed, the Electronics Industries Association's Joint Electron Device Engineering Council (JEDEC) has undertaken a project to establish a parallel write, parallel read design-for-test (DFT) interface specification for memory devices. The test interface specification includes a single input data pin providing the data to all input circuits of the test device. During a test write operation, a single data bit, received on the single input data pin, is written concurrently into all arrays of the memory device.
Subsequently, to perform the test read operation, the stored data bit is simultaneously read out of the several arrays of the memory device. The data bit read from each array is compared with an expected data bit. If all of the data bits read out of the arrays agree with the expected data bit, the state of the expected data bit is transmitted off of the memory device by way of single output pin to the tester. If one or more of the data bits read out disagree with the expected data bit, the expected data bit is inverted and transmitted out the single output pin to the tester.
Current DFT methodologies for testing narrow I/O data pin memory devices use multiple signal lines traversing the chip. Such multiple signal lines occupy valuable device area. As the number of I/O data pins increases, the number of signal lines increases proportionately. Presently, therefore, there is not an effective way to design an integrated circuit memory device that incorporate the JEDEC interface specification for testing simultaneously several wide I/O pin memory devices on a single device tester without using unnecessary device area.
In most dense designs, on-chip routing from one group of logic to another consumes 60 percent of the silicon area in row organized architectures. Traditional DFT circuitry for a wide I/O comparison only aggravates the solution through the use of multiple routing lines. Also, several new DFT tests such as x4 laser repair and x64 parallel read/write have placed constraints on the DFT architecture. A method which provides the required DFT comparisons while maintaining speed and reducing the routing area is needed.